education
- 2018 - present
-
PhD student at the University of Stuttgart, working under advisor Prof.
Dr.-Ing. Scheible at E&D in the Electronic Design Automation
research group.
- October 2017
-
Master of Science (M.Sc) in Power and Micro Electronics. Thesis at
Robert Bosch Center for Power Electronics (now Electronics &
Drives): “Concepts for Visual Input of Expert Knowledge on
Procedural IC Sizing”
- 2015 - 2017
-
Power and Micro electronics at Reutlingen University.
- August 2015
-
Bachelor of Engineering (B.Eng) in Computer Engineering. Thesis at
Eberspächer Electronics: “Implementierung und Aufbau eines
Testsystems für CAN und FlexRay Interfaces” (Implementation and
Setup of a test system for CAN and FlexRay interfaces)
- 2010 - 2015
-
Computer Engineering at University of Applied Sciences Esslingen.
experience
- November 2016 - March 2017
-
Research Assistant at Robert Bosch Center for Power Electronics in the
Electronic Design Automation research group.
- November 2014 - March 2015
-
Term Paper Project at University of Applied Sciences Esslingen:
“Entwicklung einer C++-App zur Steuering von HomeMatic-Geräten für
die Hausautomatisierung” (Implementation of a C++ app to control of
HomeMatic devices for home automation)
- February - June 2014
-
Semester abroad at Hanyang University in Seoul, South Korea.
- August 2013 - January 2014
-
Internship at Thyssen-Krupp Elevator Innovations GmbH. CAN bus message
dissector for readout of elevator controllers.
publications and awards
- November 2024
-
“A Review of Design Methodologies for Power Electronics and the
Bridge to VLSI EDA” at DMC 2024 IEEE
- November 2024
-
“Sensorless Robust Anomaly Detection of Roller Chain Systems based
on Motor Driver Data and Deep Weighted KNN” in Transactions on
Instrumentation and Measurement IEEE
- June 2024
-
“Integrating Multiple Knowledge-based Automation Methodologies into
the A/MS IC Design Flow” at SMACD 2024 IEEE
- October 2023
-
“Integration of Spectre into an ML Pipeline for Modeling Analog
Circuits” at CadenceLive Europe 2023 - Academic Track.
- September 2023
-
“Differentiable Neural Network Surrogate Models for gm/ID-based
Analog IC Sizing Optimization” at MLCAD 2023 IEEE
- January 2023
-
“Procedural- and Reinforcement-Learning-Based Automation Methods for
Analog Integrated Circuit Sizing in the Electrical Design Space” in
Advanced Design Techniques and EDA Methodologies for Analog, RF and
MM-Wave Circuit Design MDPI
- November 2022
-
“Reinforcement Learning Environment for Analog IC Sizing based on
Cadence Spectre” at CadenceLive EMEA 2022 - Academic Track.
- September 2022
-
“Deep Reinforcement Learning for Analog Circuit Sizing with an
Electrical Design Space and Sparse Rewards” at MLCAD 2022 ACM
- July 2021
-
“Machine Learning Based Procedural Circuit Sizing and DC Operating
Point Prediction” at SMACD 2021 IEEE.
- July 2019
-
“A Generic Procedural Generator for Sizing of Analog Integrated
Circuits” at PRIME 2019 IEEE DOI.
- May 2019
-
“SPAM – A SKILL Package Management System” at CDNLive EMEA 2019
- Academic Track.
- May 2018
-
“Visual Programming Environment for Cadence SKILL” at CDNLive
2018 - Academic Track.
- May 2018
-
Best Thesis Award from Cadence at CDNLive EMEA 2018.
research interest
Machine Learning, Analog Circuit Design Automation
see also
Home E&D LinkedIn
ResearchGate